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1/20 june 2002 m68aw256dl 4 mbit (256k x16) 3.0v asynchronous sram features summary n supply voltage: 2.7 to 3.6v n 256k x 16 bits sram with output enable n equal cycle and access time: 55ns n single byte read/write n low standby current n low v cc data retention: 1.5v n tri-state common i/o n automatic power down n dual chip enable for easy depth expansion figure 1. packages bga tfbga48 (zb) 7x8mm 44 1 tsop44 type ii (nd)
m68aw256dl 2/20 table of contents summary description. . . . . . . . . . . . . . . . . . ....... ..................................3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . ..................................3 figure 3. tsop connections. . . . . . . . . . . . . . . . . . . . . ..................................4 figure 4. tfbga connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . ........5 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ ......6 table 2. absolute maximum ratings. . . . . . . . . . . . . . . ..................................6 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. operating and ac measurement conditions. . ............................ ......7 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . ........................7 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................8 table 5. dc characteristics ........................................................8 operation ......................................................................9 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............9 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. address controlled, read mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. chip enable or output enable controlled, read mode ac waveforms. . . . . . . . . . . . . . 10 figure 10. chip enable or ub/lb controlled, standby mode ac waveforms . . . . . . . . ........10 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. chip enable controlled, write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. ub/lb controlled, write ac waveforms . . . ............................ .....13 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. e1 controlled, low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . 15 figure 15. e2 controlled, low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. low v cc data retention characteristics. . . . . . . . . . . . . . . .......................15 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 tsop44 type ii - 44 lead plastic thin small outline type ii, package outline ...............16 tsop 44 type ii - 44 lead plastic thin small outline type ii, package mechanical data . . . . . . . 16 tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, bottom view package outline. . . . . . . . . . . . . 17 tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data. . . . . . . . . . . . . . . . 17 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............18 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. ..............................................................19 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20 m68aw256dl summary description the m68aw256dl is a 4 mbit (4,194,304 bit) cmos sram, organized as 262,144 words by 16 bits. the device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. it requires a single 2.7 to 3.6v supply. this device has an au- tomatic power-down feature, reducing the power consumption by over 99% when deselected. the m68aw256dl is available in tfbga48 (0.75 mm pitch) and in tsop44 type ii packages. figure 2. logic diagram table 1. signal names ai05492 18 a0-a17 w dq0-dq15 v cc m68aw256dl g 16 e1 ub lb v ss e2 a0-a17 address inputs dq0-dq15 data input/output e1, e2 chip enables g output enable w write enable ub upper byte enable input lb lower byte enable input v cc supply voltage v ss ground nc not connected internally du don't use as internally connected
m68aw256dl 4/20 figure 3. tsop connections dq5 dq6 dq7 dq1 v cc v ss dq4 dq2 dq3 dq14 dq11 dq13 dq12 dq9 dq15 v ss v cc dq10 a9 a15 a13 a17 a12 a11 dq8 g a6 a3 dq0 a4 a5 a1 ai05493 m68aw256dl 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 w a16 a0 e1 e2 a8 44 39 38 37 36 35 34 33 lb ub a14 21 a10 40 43 1 42 41 a2 a7
5/20 m68aw256dl figure 4. tfbga connections (top view through package) ai05494 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 du a11 a8 nc dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 nc ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc nc v ss dq6 a16
m68aw256dl 6/20 figure 5. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratingso table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 2. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second duration. 2. up to a maximum operating v cc of 3.6v only. ai05495 row decoder a7 a17 (8) dq0 dq15 (8) column decoder i/o circuits a0 a6 w g memory array lb lb ub (8) (8) ub lb e1 e2 ex ub lb symbol parameter value unit i o (1) output current 20 ma t a ambient operating temperature 55 to 125 c t stg storage temperature 65 to 150 c v cc supply voltage 0.5 to 4.6 v v io (2) input or output voltage 0.5 to v cc +0.5 v p d power dissipation 1 w
7/20 m68aw256dl dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions figure 6. ac measurement i/o waveform figure 7. ac measurement load circuit parameter m68aw256ml v cc supply voltage 2.7 to 3.6v ambient operating temperature range 1 0 to 70 c range 6 40 to 85 c load capacitance (c l ) 30pf output circuit protection resistance (r 1 ) 3.0k w load resistance (r 2 ) 3.1k w input rise and fall times 1ns/v input pulse voltages 0tov cc input and output timing ref. voltages v cc /2 output transition timing ref. voltages v rl = 0.3v cc ;v rh =0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc i/o transition timing reference voltage 0v 0.7v cc 0.3v cc ai05832 v cc out c l includes probe and 1 ttlcapacitance device under test c l r 1 r 2
m68aw256dl 8/20 table 4. capacitance note: 1. sampled only, not 100% tested. 2. at t a =25 c, f = 1 mhz, v cc = 3.0v. 3. outputs deselected. table 5. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e1 = v il ,e2=v ih , lb or/and ub = v il ,v in =v il or v ih . 3. e1 0.2v or e2 v cc 0.2v, lb or/and ub 0.2v, v in 0.2v or v in v cc 0.2v. 4. output disabled. symbol parameter (1,2) test conditio n min max unit c in input capacitance on all pins (except dq) v in =0v 8pf c out (3) output capacitance v out =0v 10 pf symbol parameter test condition min typ max unit i cc1 (1,2) operating supply current v cc = 3.6v, f = 1/t avav , i out = 0ma 70ns 20 ma 55ns 26 ma i cc2 (3) operating supply current v cc = 3.6v, f = 1mhz, i out =0ma 2ma i sb standby supply current cmos v cc = 3.6v, f = 0, e1 v cc 0.2v or e2 0.2v or lb=ub v cc 0.2v 510 m a i li input leakage current 0v v in v cc 1 1 m a i lo (4) output leakage current 0v v out v cc 1 1 m a v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage 0.3 0.6 v v oh output high voltage i oh = 1.0ma 2.4 v v ol output low voltage i ol = 2.1ma 0.4 v
9/20 m68aw256dl operation the m68aw256dl has a chip enable power down feature which invokes an automatic standby mode whenever chip enable is de-asserted (e1 = high) or chip select is asserted (e2 = low), or ub/ lb are de-asserted (ub/lb = high). an output en- able (g) signal provides a high speed tri-state con- trol, allowing fast read/write cycles to be achieved with the common i/o data bus. operational modes are determined by device control inputs w, e1, lb and ub as summarized in the operating modes ta- ble (see table 6). table 6. operating modes note: x = v ih or v il . read mode the m68aw256dl, when chip select (e2) is high, is in the read mode whenever write enable (w) is high with output enable (g) low, and chip enable (e1) is asserted. this provides access to data from eight or sixteen, depending on the status of the signal ub and lb, of the 4,194,304 locations in the static memory array, specified by the 18 ad- dress inputs. valid data will be available at the eight or sixteen output pins within t avqv after the last stable address, providing g is low and e1 is low. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv ,t glqv or t blqv ) rather than the address. data out may be indeter- minate at t elqx ,t glqx and t blqx , but data lines will always be valid at t avqv . figure 8. address controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high, ub = low and/or lb = low. operation e1 e2 w g lb ub dq0-dq7 dq8-dq15 power deselected v ih x x x x x hi-z hi-z standby (i sb ) deselected x v il x x x x hi-z hi-z standby (i sb ) deselected x x x x v ih v ih hi-z hi-z standby (i sb ) lower byte read v il v ih v ih v il v il v ih data output hi-z active (i cc ) lower byte write v il v ih v il x v il v ih data input hi-z active (i cc ) output disabled v il v ih v ih v ih x x hi-z hi-z active (i cc ) upper byte read v il v ih v ih v il v ih v il hi-z data output active (i cc ) upper byte write v il v ih v il x v ih v il hi-z data input active (i cc ) word read v il v ih v ih v il v il v il data output data output active (i cc ) word write v il v ih v il x v il v il data input data input active (i cc ) ai03956 tavav tavqv taxqx a0-a17 dq0-dq7 and/or dq8-dq15 valid data valid
m68aw256dl 10/20 figure 9. chip enable or output enable controlled, read mode ac waveforms. note: writ e enable (w) = high. figure 10. chip enable or ub/lb controlled, standby mode ac waveforms ai05496 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a17 e1 g dq0-dq15 valid tblqv tblqx tbhqz ub, lb e2 ai05497 tpd i cc tpu i sb 50% e1, ub, lb e2
11/20 m68aw256dl table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ghqz is less than t glqx ,t bhqz is less than t blqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. tested initially and after any design or process changes that may affect these parameters. symbol parameter m68aw256dl unit 55 70 t avav read cycle time min 55 70 ns t avqv address valid to output valid max 55 70 ns t axqx (1) data hold from address change min 5 5 ns t bhqz (2,3) upper/lower byte enable high to output hi-z max 20 25 ns t blqv upper/lower byte enable low to output valid max 55 70 ns t blqx (1) upper/lower byte enable low to output transition min 5 5 ns t ehqz (2,3) chip enable high to output hi-z max 20 25 ns t elqv chip enable low to output valid max 55 70 ns t elqx (1) chip enable low to output transition min 5 5 ns t ghqz (2,3) output enable high to output hi-z max 20 25 ns t glqv output enable low to output valid max 25 35 ns t glqx (2) output enable low to output transition min 5 5 ns t pd (4) chip enable or ub/lb high to power down max 0 0 ns t pu (4) chip enable or ub/lb low to power up min 55 70 ns
m68aw256dl 12/20 write mode the m68aw256dl, when chip select (e2) is high, is in the write mode whenever the w and e1 are low. either the chip enable input (e1) or the write enable input (w) must be de-asserted dur- ing address transitions for subsequent write cy- cles. when e1 or w is low, and ub or lb is low, write cycle begins on the w or e1 falling edge. when e1 and w are low, and ub = lb = high, write cycle begins on the first falling edge of ub or lb. therefore, address setup time is referenced to write enable, chip enables and ub/lb as t avwl , t avel and t avbl respectively, and is determined by the latter occurring falling edge. the write cycle can be terminated by the earlier rising edge of e1, w, ub and lb. if the output is enabled (e1 = low, e2 = high, g = low, lb or ub = low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e1 or for t dvbh before the rising edge of ub/lb, whichever occurs first, and remain valid for t whdx , t ehdx and t bhdx respectively. figure 11. write enable controlled, write ac waveforms ai05498 tavav twhax tdvwh data input a0-a17 e1 w dq0-dq15 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx tblbh ub, lb e2 telwh
13/20 m68aw256dl figure 12. chip enable controlled, write ac waveforms figure 13. ub/lb controlled, write ac waveforms note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai05425 tavav tehax tdveh a0-a17 e1 w dq0-dq15 valid taveh tavel tavwl teleh tehdx data input tblbh ub, lb e2 twleh ai05426 tavav tbhax tdvbh data input a0-a17 e1 w dq0-dq15 valid tavbh tavwl twlqz tbhdx tblbh ub, lb data (1) tavbl e2 twlbh
m68aw256dl 14/20 table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. symbol parameter m68aw256dl unit 55 70 t avav write cycle time min 55 70 ns t avbh address valid to lb, ub high min 45 60 ns t avbl addess valid to lb, ub low min 0 0 ns t aveh address valid to chip enable high min 45 60 ns t avel address valid to chip enable low min 0 0 ns t avwh address valid to write enable high min 45 60 ns t avwl address valid to write enable low min 0 0 ns t bhax lb, ub high to address transition min 0 0 ns t bhdx lb, ub high to input transition min 0 0 ns t blbh lb, ub low to lb, ub high min 45 60 ns t bleh lb, ub low to chip enable high min 45 60 ns t blwh lb, ub low to write enable high min 45 60 ns t dvbh input valid to lb, ub high min 25 30 ns t dveh input valid to chip enable high min 25 30 ns t dvwh input valid to write enable high min 25 30 ns t ehax chip enable high to address transition min 0 0 ns t ehdx chip enable high to input transition min 0 0 ns t elbh chip enable low to lb, ub high min 45 60 ns t eleh chip enable low to chip enable high min 45 60 ns t elwh chip enable low to write enable high min 45 60 ns t whax write enable high to address transition min 0 0 ns t whdx write enable high to input transition min 0 0 ns t whqx (1) write enable high to output transition min 5 5 ns t wlbh write enable low to lb, ub high min 45 60 ns t wleh write enable low to chip enable high min 45 60 ns t wlqz (1,2) write enable low to output hi-z max 20 20 ns t wlwh write enable low to write enable high min 45 60 ns
15/20 m68aw256dl figure 14. e1 controlled, low v cc data retention ac waveforms figure 15. e2 controlled, low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih v cc 0.2v or v il 0.2v. 2. tested initially and after any design or process changes that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. symbol parameter test condition min typ max unit i ccdr (1) supply current (data retention) v cc = 1.5v, e1 v cc 0.2v or e2 0.2v or ub = lb v cc 0.2v, f=0 4.5 9 m a t cdr (1,2) chip deselected to data retention time 0ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e1 v cc 0.2v or e2 0.2v or ub = lb v cc 0.2v, f = 0 1.5 v ai05456 data retention mode tr 3.6v tcdr v cc 2.7v v dr > 1.5v e1, ub/lb e1 v dr 0.2v or ub=lb > v dr 0.2v ai05457 data retention mode 3.6v v cc 2.7v v dr > 1.5v e2 0.2v tcdr e2 tr
m68aw256dl 16/20 package mechanical figure 16. tsop44 type ii - 44 lead plastic thin small outline type ii, package outline note: drawing is not to scale. table 10. tsop 44 type ii - 44 lead plastic thin small outline type ii, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 b 0.350 0.0138 c 0.120 0.210 0.0047 0.0083 d 18.410 0.7248 e 11.760 0.4630 e1 10.160 0.4000 e 0.800 0.0315 l 0.500 0.400 0.600 0.0197 0.0157 0.0236 zd 0.805 0.0317 alfa 0 5 0 5 cp 0.100 0.0039 n44 44 tsop-d n 1 cp a l a1 a n/2 d e b e1 e c a2 zd
17/20 m68aw256dl figure 17. tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, bottom view package outline note: drawing is not to scale. table 11. tfbga48 7x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.010 1.200 0.0398 0.0472 a1 0.260 0.0102 a2 0.950 0.0374 b 0.400 0.300 0.500 0.0157 0.0118 0.0197 d 7.000 6.900 7.100 0.2756 0.2717 0.2795 d1 3.750 0.1476 ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.250 0.2067 e 0.750 0.0295 fd 1.625 0.0640 fe 1.375 0.0541 sd 0.375 0.0148 se 0.375 0.0148 e1 e d1 d eb a2 a1 a bga-z22 ddd fd fe sd se e ball oa1o
m68aw256dl 18/20 part numbering table 12. ordering information scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m68aw256 d l 55 zb 6 t device type m68 mode a = asynchronous operating voltage w = 2.7 to 3.6v array organization 256 = 4 mbit (256k x16) optio n 1 d = 2 chip enable; write and standby from ub and lb optio n 2 l = low leakage speed class 55 = 55 ns 70 = 70 ns package nd = tsop 44 type ii zb = tfbga48: 0.75 mm pitch operative temperature 1=0to70 c 6=40to85 c shipping t = tape & reel packing
19/20 m68aw256dl revision history table 13. document revision history date version revision details february 2002 -01 first issue 14-mar-2002 -02 tables 3, 5, 7 and 9 clarified figures 3, 8, 9, 11, 12, 13 and 14 clarified 07-jun-2002 -03 i ccdr clarified (table 9) i sb clarified (table 5)
m68aw256dl 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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